\doxysection{core\+\_\+cm33.\+h}
\hypertarget{core__cm33_8h_source}{}\label{core__cm33_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/core\_cm33.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/CMSIS/Include/core\_cm33.h}}
\mbox{\hyperlink{core__cm33_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{00531\ \ \ \_\_OM\ \ uint32\_t\ ICIALLU;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
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\DoxyCodeLine{00533\ \ \ \_\_OM\ \ uint32\_t\ ICIMVAU;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
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\DoxyCodeLine{00541\ \}\ \mbox{\hyperlink{struct_s_c_b___type}{SCB\_Type}};}
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\DoxyCodeLine{00556\ \textcolor{preprocessor}{\#define\ SCB\_CPUID\_REVISION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00567\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_PENDNMICLR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_PENDNMICLR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00594\ \textcolor{preprocessor}{\#define\ SCB\_ICSR\_RETTOBASE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_ICSR\_RETTOBASE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00604\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00605\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTKEY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_AIRCR\_VECTKEY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00611\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_ENDIANESS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_ENDIANESS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00613\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 14U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00614\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_PRIS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00616\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_BFHFNMINS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 13U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00617\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_BFHFNMINS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_BFHFNMINS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00619\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIGROUP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00620\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_PRIGROUP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_AIRCR\_PRIGROUP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00622\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQS\_Pos\ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00623\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQS\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_SYSRESETREQS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00625\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQ\_Pos\ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00626\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_SYSRESETREQ\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_SYSRESETREQ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00628\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTCLRACTIVE\_Pos\ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00629\ \textcolor{preprocessor}{\#define\ SCB\_AIRCR\_VECTCLRACTIVE\_Msk\ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_AIRCR\_VECTCLRACTIVE\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00632\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SEVONPEND\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00633\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SEVONPEND\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SEVONPEND\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00635\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEPS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00636\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEPS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPDEEPS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00638\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00639\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPDEEP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPDEEP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00641\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPONEXIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00642\ \textcolor{preprocessor}{\#define\ SCB\_SCR\_SLEEPONEXIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SCR\_SLEEPONEXIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00644\ \textcolor{comment}{/*\ SCB\ Configuration\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00645\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00646\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_BP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00648\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_IC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00649\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_IC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_IC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00651\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00652\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_DC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00654\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_STKOFHFNMIGN\_Pos\ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00655\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_STKOFHFNMIGN\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_STKOFHFNMIGN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00657\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BFHFNMIGN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00658\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_BFHFNMIGN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_BFHFNMIGN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00660\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DIV\_0\_TRP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00661\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_DIV\_0\_TRP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_DIV\_0\_TRP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00663\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_UNALIGN\_TRP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00664\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_UNALIGN\_TRP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_UNALIGN\_TRP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00666\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_USERSETMPEND\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00667\ \textcolor{preprocessor}{\#define\ SCB\_CCR\_USERSETMPEND\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CCR\_USERSETMPEND\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00670\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_HARDFAULTPENDED\_Pos\ \ \ \ \ \ 21U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00671\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_HARDFAULTPENDED\_Msk\ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_HARDFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00673\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTPENDED\_Pos\ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00674\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTPENDED\_Msk\ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SECUREFAULTPENDED\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00676\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTENA\_Pos\ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00677\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTENA\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SECUREFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00679\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00680\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00682\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00683\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00685\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTENA\_Pos\ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00686\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTENA\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MEMFAULTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00688\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLPENDED\_Pos\ \ \ \ \ \ \ \ \ 15U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00689\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLPENDED\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SVCALLPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00691\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTPENDED\_Pos\ \ \ \ \ \ \ 14U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00692\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00694\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTPENDED\_Pos\ \ \ \ \ \ \ 13U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00695\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MEMFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00697\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTPENDED\_Pos\ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00698\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTPENDED\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTPENDED\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00700\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SYSTICKACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00701\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SYSTICKACT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SYSTICKACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00703\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_PENDSVACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00704\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_PENDSVACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_PENDSVACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00706\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MONITORACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00707\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MONITORACT\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_MONITORACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00709\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00710\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SVCALLACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SVCALLACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00712\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_NMIACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00713\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_NMIACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_NMIACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00715\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTACT\_Pos\ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00716\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_SECUREFAULTACT\_Msk\ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_SECUREFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00718\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00719\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_USGFAULTACT\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_USGFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00721\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_HARDFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00722\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_HARDFAULTACT\_Msk\ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_HARDFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00724\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00725\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_BUSFAULTACT\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_SHCSR\_BUSFAULTACT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00727\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTACT\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00728\ \textcolor{preprocessor}{\#define\ SCB\_SHCSR\_MEMFAULTACT\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_SHCSR\_MEMFAULTACT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00731\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_USGFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00732\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_USGFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFFFUL\ <<\ SCB\_CFSR\_USGFAULTSR\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00734\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BUSFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00735\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BUSFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ SCB\_CFSR\_BUSFAULTSR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00736\ }
\DoxyCodeLine{00737\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MEMFAULTSR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00738\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MEMFAULTSR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ SCB\_CFSR\_MEMFAULTSR\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00740\ \textcolor{comment}{/*\ MemManage\ Fault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00741\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MMARVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 7U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00742\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MMARVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MMARVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00743\ }
\DoxyCodeLine{00744\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MLSPERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 5U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00745\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MLSPERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MLSPERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00746\ }
\DoxyCodeLine{00747\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 4U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00748\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00749\ }
\DoxyCodeLine{00750\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MUNSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00751\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_MUNSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_MUNSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00753\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DACCVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00754\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DACCVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_DACCVIOL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00755\ }
\DoxyCodeLine{00756\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IACCVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_SHCSR\_MEMFAULTACT\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00757\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IACCVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_CFSR\_IACCVIOL\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00758\ }
\DoxyCodeLine{00759\ \textcolor{comment}{/*\ BusFault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00760\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BFARVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 7U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00761\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_BFARVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_BFARVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00762\ }
\DoxyCodeLine{00763\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_LSPERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 5U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00764\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_LSPERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_LSPERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00765\ }
\DoxyCodeLine{00766\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 4U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00767\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_STKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00768\ }
\DoxyCodeLine{00769\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNSTKERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00770\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNSTKERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNSTKERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00771\ }
\DoxyCodeLine{00772\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IMPRECISERR\_Pos\ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 2U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00773\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IMPRECISERR\_Msk\ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_IMPRECISERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00774\ }
\DoxyCodeLine{00775\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_PRECISERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00776\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_PRECISERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_PRECISERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00777\ }
\DoxyCodeLine{00778\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IBUSERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_BUSFAULTSR\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00779\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_IBUSERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_IBUSERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00780\ }
\DoxyCodeLine{00781\ \textcolor{comment}{/*\ UsageFault\ Status\ Register\ (part\ of\ SCB\ Configurable\ Fault\ Status\ Register)\ */}}
\DoxyCodeLine{00782\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DIVBYZERO\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 9U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00783\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_DIVBYZERO\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_DIVBYZERO\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00784\ }
\DoxyCodeLine{00785\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNALIGNED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 8U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00786\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNALIGNED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNALIGNED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00787\ }
\DoxyCodeLine{00788\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKOF\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 4U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00789\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_STKOF\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_STKOF\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00790\ }
\DoxyCodeLine{00791\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_NOCP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 3U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00792\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_NOCP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_NOCP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00793\ }
\DoxyCodeLine{00794\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVPC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 2U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00795\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVPC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_INVPC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00796\ }
\DoxyCodeLine{00797\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVSTATE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 1U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00798\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_INVSTATE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_INVSTATE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00799\ }
\DoxyCodeLine{00800\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNDEFINSTR\_Pos\ \ \ \ \ \ \ \ \ \ \ (SCB\_CFSR\_USGFAULTSR\_Pos\ +\ 0U)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00801\ \textcolor{preprocessor}{\#define\ SCB\_CFSR\_UNDEFINSTR\_Msk\ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_CFSR\_UNDEFINSTR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00802\ }
\DoxyCodeLine{00803\ \textcolor{comment}{/*\ SCB\ Hard\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00804\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_DEBUGEVT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00805\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_DEBUGEVT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_DEBUGEVT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00806\ }
\DoxyCodeLine{00807\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_FORCED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00808\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_FORCED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_FORCED\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00809\ }
\DoxyCodeLine{00810\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_VECTTBL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00811\ \textcolor{preprocessor}{\#define\ SCB\_HFSR\_VECTTBL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_HFSR\_VECTTBL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00812\ }
\DoxyCodeLine{00813\ \textcolor{comment}{/*\ SCB\ Debug\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{00814\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_EXTERNAL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00815\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_EXTERNAL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_EXTERNAL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00816\ }
\DoxyCodeLine{00817\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_VCATCH\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00818\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_VCATCH\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_VCATCH\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00819\ }
\DoxyCodeLine{00820\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_DWTTRAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00821\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_DWTTRAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_DWTTRAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00822\ }
\DoxyCodeLine{00823\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_BKPT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00824\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_BKPT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_DFSR\_BKPT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00825\ }
\DoxyCodeLine{00826\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_HALTED\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00827\ \textcolor{preprocessor}{\#define\ SCB\_DFSR\_HALTED\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_DFSR\_HALTED\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00828\ }
\DoxyCodeLine{00829\ \textcolor{comment}{/*\ SCB\ Non-\/Secure\ Access\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{00830\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CP11\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 11U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00831\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CP11\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_NSACR\_CP11\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00833\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CP10\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00834\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CP10\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SCB\_NSACR\_CP10\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{00836\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CPn\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00837\ \textcolor{preprocessor}{\#define\ SCB\_NSACR\_CPn\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SCB\_NSACR\_CPn\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00838\ }
\DoxyCodeLine{00839\ \textcolor{comment}{/*\ SCB\ Cache\ Level\ ID\ Register\ Definitions\ */}}
\DoxyCodeLine{00840\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOUU\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00841\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOUU\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CLIDR\_LOUU\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00842\ }
\DoxyCodeLine{00843\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00844\ \textcolor{preprocessor}{\#define\ SCB\_CLIDR\_LOC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CLIDR\_LOC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00845\ }
\DoxyCodeLine{00846\ \textcolor{comment}{/*\ SCB\ Cache\ Type\ Register\ Definitions\ */}}
\DoxyCodeLine{00847\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_FORMAT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00848\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_FORMAT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (7UL\ <<\ SCB\_CTR\_FORMAT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00849\ }
\DoxyCodeLine{00850\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_CWG\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00851\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_CWG\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ SCB\_CTR\_CWG\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{00852\ }
\DoxyCodeLine{00853\ \textcolor{preprocessor}{\#define\ SCB\_CTR\_ERG\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01205\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01207\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_FOLDEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 21U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01208\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_FOLDEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_FOLDEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01210\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_LSUEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01211\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_LSUEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_LSUEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01213\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SLEEPEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ 19U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01214\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SLEEPEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_SLEEPEVTENA\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01216\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 18U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01217\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_EXCEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01219\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CPIEVTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 17U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01220\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CPIEVTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CPIEVTENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01222\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCTRCENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01223\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_EXCTRCENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_EXCTRCENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01225\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_PCSAMPLENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01226\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_PCSAMPLENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_PCSAMPLENA\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01228\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SYNCTAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01229\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_SYNCTAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ DWT\_CTRL\_SYNCTAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01231\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCTAP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01232\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCTAP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_CTRL\_CYCTAP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01234\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTINIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01235\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTINIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_POSTINIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01237\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTPRESET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01238\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_POSTPRESET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ DWT\_CTRL\_POSTPRESET\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01240\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCCNTENA\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01241\ \textcolor{preprocessor}{\#define\ DWT\_CTRL\_CYCCNTENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ DWT\_CTRL\_CYCCNTENA\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01243\ \textcolor{comment}{/*\ DWT\ CPI\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01244\ \textcolor{preprocessor}{\#define\ DWT\_CPICNT\_CPICNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01245\ \textcolor{preprocessor}{\#define\ DWT\_CPICNT\_CPICNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_CPICNT\_CPICNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01247\ \textcolor{comment}{/*\ DWT\ Exception\ Overhead\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01248\ \textcolor{preprocessor}{\#define\ DWT\_EXCCNT\_EXCCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01249\ \textcolor{preprocessor}{\#define\ DWT\_EXCCNT\_EXCCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_EXCCNT\_EXCCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01252\ \textcolor{preprocessor}{\#define\ DWT\_SLEEPCNT\_SLEEPCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01253\ \textcolor{preprocessor}{\#define\ DWT\_SLEEPCNT\_SLEEPCNT\_Msk\ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_SLEEPCNT\_SLEEPCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01256\ \textcolor{preprocessor}{\#define\ DWT\_LSUCNT\_LSUCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01257\ \textcolor{preprocessor}{\#define\ DWT\_LSUCNT\_LSUCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_LSUCNT\_LSUCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01259\ \textcolor{comment}{/*\ DWT\ Folded-\/instruction\ Count\ Register\ Definitions\ */}}
\DoxyCodeLine{01260\ \textcolor{preprocessor}{\#define\ DWT\_FOLDCNT\_FOLDCNT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01261\ \textcolor{preprocessor}{\#define\ DWT\_FOLDCNT\_FOLDCNT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ DWT\_FOLDCNT\_FOLDCNT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01263\ \textcolor{comment}{/*\ DWT\ Comparator\ Function\ Register\ Definitions\ */}}
\DoxyCodeLine{01264\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_ID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01265\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_ID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FUL\ <<\ DWT\_FUNCTION\_ID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01267\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCHED\_Pos\ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01268\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCHED\_Msk\ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_MATCHED\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01270\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVSIZE\_Pos\ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01271\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_DATAVSIZE\_Msk\ \ \ \ \ \ \ \ \ (0x3UL\ <<\ DWT\_FUNCTION\_DATAVSIZE\_Pos)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01273\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_ACTION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01274\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_ACTION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ DWT\_FUNCTION\_ACTION\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01276\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCH\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01277\ \textcolor{preprocessor}{\#define\ DWT\_FUNCTION\_MATCH\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ DWT\_FUNCTION\_MATCH\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01278\ \ \textcolor{comment}{/*\ end\ of\ group\ CMSIS\_DWT\ */}}
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\DoxyCodeLine{01292\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01293\ \{}
\DoxyCodeLine{01294\ \ \ \_\_IM\ \ uint32\_t\ SSPSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01295\ \ \ \_\_IOM\ uint32\_t\ CSPSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01296\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[2U];}
\DoxyCodeLine{01297\ \ \ \_\_IOM\ uint32\_t\ ACPR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01298\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED1[55U];}
\DoxyCodeLine{01299\ \ \ \_\_IOM\ uint32\_t\ SPPR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01300\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED2[131U];}
\DoxyCodeLine{01301\ \ \ \_\_IM\ \ uint32\_t\ FFSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01302\ \ \ \_\_IOM\ uint32\_t\ FFCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01303\ \ \ \_\_IOM\ uint32\_t\ PSCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01304\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED3[759U];}
\DoxyCodeLine{01305\ \ \ \_\_IM\ \ uint32\_t\ TRIGGER;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01306\ \ \ \_\_IM\ \ uint32\_t\ ITFTTD0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01307\ \ \ \_\_IOM\ uint32\_t\ ITATBCTR2;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01308\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[1U];}
\DoxyCodeLine{01309\ \ \ \_\_IM\ \ uint32\_t\ ITATBCTR0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01310\ \ \ \_\_IM\ \ uint32\_t\ ITFTTD1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01311\ \ \ \_\_IOM\ uint32\_t\ ITCTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01312\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED5[39U];}
\DoxyCodeLine{01313\ \ \ \_\_IOM\ uint32\_t\ CLAIMSET;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01314\ \ \ \_\_IOM\ uint32\_t\ CLAIMCLR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01315\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED7[8U];}
\DoxyCodeLine{01316\ \ \ \_\_IM\ \ uint32\_t\ DEVID;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01317\ \ \ \_\_IM\ \ uint32\_t\ DEVTYPE;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01318\ \}\ \mbox{\hyperlink{struct_t_p_i___type}{TPI\_Type}};}
\DoxyCodeLine{01319\ }
\DoxyCodeLine{01320\ \textcolor{comment}{/*\ TPI\ Asynchronous\ Clock\ Prescaler\ Register\ Definitions\ */}}
\DoxyCodeLine{01321\ \textcolor{preprocessor}{\#define\ TPI\_ACPR\_PRESCALER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01322\ \textcolor{preprocessor}{\#define\ TPI\_ACPR\_PRESCALER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFUL\ }\textcolor{comment}{/*<<\ TPI\_ACPR\_PRESCALER\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01324\ \textcolor{comment}{/*\ TPI\ Selected\ Pin\ Protocol\ Register\ Definitions\ */}}
\DoxyCodeLine{01325\ \textcolor{preprocessor}{\#define\ TPI\_SPPR\_TXMODE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01326\ \textcolor{preprocessor}{\#define\ TPI\_SPPR\_TXMODE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ }\textcolor{comment}{/*<<\ TPI\_SPPR\_TXMODE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01328\ \textcolor{comment}{/*\ TPI\ Formatter\ and\ Flush\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01329\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtNonStop\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01330\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtNonStop\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_FtNonStop\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01332\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_TCPresent\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01333\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_TCPresent\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_TCPresent\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01335\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtStopped\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01336\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FtStopped\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFSR\_FtStopped\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01338\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FlInProg\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01339\ \textcolor{preprocessor}{\#define\ TPI\_FFSR\_FlInProg\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_FFSR\_FlInProg\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01341\ \textcolor{comment}{/*\ TPI\ Formatter\ and\ Flush\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01342\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_TrigIn\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01343\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_TrigIn\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFCR\_TrigIn\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01345\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_FOnMan\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01346\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_FOnMan\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFCR\_FOnMan\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01348\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_EnFCont\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01349\ \textcolor{preprocessor}{\#define\ TPI\_FFCR\_EnFCont\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ <<\ TPI\_FFCR\_EnFCont\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01351\ \textcolor{comment}{/*\ TPI\ TRIGGER\ Register\ Definitions\ */}}
\DoxyCodeLine{01352\ \textcolor{preprocessor}{\#define\ TPI\_TRIGGER\_TRIGGER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01353\ \textcolor{preprocessor}{\#define\ TPI\_TRIGGER\_TRIGGER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (0x1UL\ }\textcolor{comment}{/*<<\ TPI\_TRIGGER\_TRIGGER\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01506\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_HFNMIENA\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ MPU\_CTRL\_HFNMIENA\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01507\ }
\DoxyCodeLine{01508\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01509\ \textcolor{preprocessor}{\#define\ MPU\_CTRL\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_CTRL\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01510\ }
\DoxyCodeLine{01511\ \textcolor{comment}{/*\ MPU\ Region\ Number\ Register\ Definitions\ */}}
\DoxyCodeLine{01512\ \textcolor{preprocessor}{\#define\ MPU\_RNR\_REGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01513\ \textcolor{preprocessor}{\#define\ MPU\_RNR\_REGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ MPU\_RNR\_REGION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01514\ }
\DoxyCodeLine{01515\ \textcolor{comment}{/*\ MPU\ Region\ Base\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01516\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_BASE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01517\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_BASE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFFFFUL\ <<\ MPU\_RBAR\_BASE\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01518\ }
\DoxyCodeLine{01519\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_SH\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01520\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_SH\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ MPU\_RBAR\_SH\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01521\ }
\DoxyCodeLine{01522\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_AP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01523\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_AP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x3UL\ <<\ MPU\_RBAR\_AP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01524\ }
\DoxyCodeLine{01525\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_XN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01526\ \textcolor{preprocessor}{\#define\ MPU\_RBAR\_XN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (01UL\ }\textcolor{comment}{/*<<\ MPU\_RBAR\_XN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01527\ }
\DoxyCodeLine{01528\ \textcolor{comment}{/*\ MPU\ Region\ Limit\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01529\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_LIMIT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01530\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_LIMIT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFFFFUL\ <<\ MPU\_RLAR\_LIMIT\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01531\ }
\DoxyCodeLine{01532\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_AttrIndx\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01533\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_AttrIndx\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7UL\ <<\ MPU\_RLAR\_AttrIndx\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01534\ }
\DoxyCodeLine{01535\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_EN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01536\ \textcolor{preprocessor}{\#define\ MPU\_RLAR\_EN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ MPU\_RLAR\_EN\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01537\ }
\DoxyCodeLine{01538\ \textcolor{comment}{/*\ MPU\ Memory\ Attribute\ Indirection\ Register\ 0\ Definitions\ */}}
\DoxyCodeLine{01539\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr3\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01540\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr3\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR0\_Attr3\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01541\ }
\DoxyCodeLine{01542\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr2\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01543\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr2\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR0\_Attr2\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01544\ }
\DoxyCodeLine{01545\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr1\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01546\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr1\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR0\_Attr1\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01547\ }
\DoxyCodeLine{01548\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr0\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01549\ \textcolor{preprocessor}{\#define\ MPU\_MAIR0\_Attr0\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ MPU\_MAIR0\_Attr0\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01550\ }
\DoxyCodeLine{01551\ \textcolor{comment}{/*\ MPU\ Memory\ Attribute\ Indirection\ Register\ 1\ Definitions\ */}}
\DoxyCodeLine{01552\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr7\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01553\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr7\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR1\_Attr7\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01554\ }
\DoxyCodeLine{01555\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr6\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01556\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr6\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR1\_Attr6\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01557\ }
\DoxyCodeLine{01558\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr5\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01559\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr5\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ <<\ MPU\_MAIR1\_Attr5\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01560\ }
\DoxyCodeLine{01561\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr4\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01562\ \textcolor{preprocessor}{\#define\ MPU\_MAIR1\_Attr4\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ MPU\_MAIR1\_Attr4\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01563\ }
\DoxyCodeLine{01565\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01566\ }
\DoxyCodeLine{01567\ }
\DoxyCodeLine{01568\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{01575\ }
\DoxyCodeLine{01579\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01580\ \{}
\DoxyCodeLine{01581\ \ \ \_\_IOM\ uint32\_t\ CTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01582\ \ \ \_\_IM\ \ uint32\_t\ TYPE;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01583\ \textcolor{preprocessor}{\#if\ defined\ (\_\_SAUREGION\_PRESENT)\ \&\&\ (\_\_SAUREGION\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{01584\ \ \ \_\_IOM\ uint32\_t\ RNR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01585\ \ \ \_\_IOM\ uint32\_t\ RBAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01586\ \ \ \_\_IOM\ uint32\_t\ RLAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01587\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{01588\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[3];}
\DoxyCodeLine{01589\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01590\ \ \ \_\_IOM\ uint32\_t\ SFSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01591\ \ \ \_\_IOM\ uint32\_t\ SFAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01592\ \}\ SAU\_Type;}
\DoxyCodeLine{01593\ }
\DoxyCodeLine{01594\ \textcolor{comment}{/*\ SAU\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01595\ \textcolor{preprocessor}{\#define\ SAU\_CTRL\_ALLNS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01596\ \textcolor{preprocessor}{\#define\ SAU\_CTRL\_ALLNS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_CTRL\_ALLNS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01597\ }
\DoxyCodeLine{01598\ \textcolor{preprocessor}{\#define\ SAU\_CTRL\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01599\ \textcolor{preprocessor}{\#define\ SAU\_CTRL\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SAU\_CTRL\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01600\ }
\DoxyCodeLine{01601\ \textcolor{comment}{/*\ SAU\ Type\ Register\ Definitions\ */}}
\DoxyCodeLine{01602\ \textcolor{preprocessor}{\#define\ SAU\_TYPE\_SREGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01603\ \textcolor{preprocessor}{\#define\ SAU\_TYPE\_SREGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ SAU\_TYPE\_SREGION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01604\ }
\DoxyCodeLine{01605\ \textcolor{preprocessor}{\#if\ defined\ (\_\_SAUREGION\_PRESENT)\ \&\&\ (\_\_SAUREGION\_PRESENT\ ==\ 1U)}}
\DoxyCodeLine{01606\ \textcolor{comment}{/*\ SAU\ Region\ Number\ Register\ Definitions\ */}}
\DoxyCodeLine{01607\ \textcolor{preprocessor}{\#define\ SAU\_RNR\_REGION\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01608\ \textcolor{preprocessor}{\#define\ SAU\_RNR\_REGION\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFFUL\ }\textcolor{comment}{/*<<\ SAU\_RNR\_REGION\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01609\ }
\DoxyCodeLine{01610\ \textcolor{comment}{/*\ SAU\ Region\ Base\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01611\ \textcolor{preprocessor}{\#define\ SAU\_RBAR\_BADDR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01612\ \textcolor{preprocessor}{\#define\ SAU\_RBAR\_BADDR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFFFFUL\ <<\ SAU\_RBAR\_BADDR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01613\ }
\DoxyCodeLine{01614\ \textcolor{comment}{/*\ SAU\ Region\ Limit\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01615\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_LADDR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01616\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_LADDR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x7FFFFFFUL\ <<\ SAU\_RLAR\_LADDR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01617\ }
\DoxyCodeLine{01618\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_NSC\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01619\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_NSC\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_RLAR\_NSC\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01620\ }
\DoxyCodeLine{01621\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_ENABLE\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01622\ \textcolor{preprocessor}{\#define\ SAU\_RLAR\_ENABLE\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ SAU\_RLAR\_ENABLE\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01623\ }
\DoxyCodeLine{01624\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_SAUREGION\_PRESENT)\ \&\&\ (\_\_SAUREGION\_PRESENT\ ==\ 1U)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01625\ }
\DoxyCodeLine{01626\ \textcolor{comment}{/*\ Secure\ Fault\ Status\ Register\ Definitions\ */}}
\DoxyCodeLine{01627\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_LSERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01628\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_LSERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_LSERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01629\ }
\DoxyCodeLine{01630\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_SFARVALID\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01631\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_SFARVALID\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_SFARVALID\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01632\ }
\DoxyCodeLine{01633\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_LSPERR\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01634\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_LSPERR\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_LSPERR\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01635\ }
\DoxyCodeLine{01636\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVTRAN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01637\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVTRAN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_INVTRAN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01638\ }
\DoxyCodeLine{01639\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_AUVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01640\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_AUVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_AUVIOL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01641\ }
\DoxyCodeLine{01642\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01643\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_INVER\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01644\ }
\DoxyCodeLine{01645\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVIS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01646\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVIS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ SAU\_SFSR\_INVIS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01647\ }
\DoxyCodeLine{01648\ \textcolor{preprocessor}{\#define\ SAU\_SFSR\_INVEP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01666\ \{}
\DoxyCodeLine{01667\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED0[1U];}
\DoxyCodeLine{01668\ \ \ \_\_IOM\ uint32\_t\ FPCCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01669\ \ \ \_\_IOM\ uint32\_t\ FPCAR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01670\ \ \ \_\_IOM\ uint32\_t\ FPDSCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01671\ \ \ \_\_IM\ \ uint32\_t\ MVFR0;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01672\ \ \ \_\_IM\ \ uint32\_t\ MVFR1;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01673\ \}\ \mbox{\hyperlink{struct_f_p_u___type}{FPU\_Type}};}
\DoxyCodeLine{01674\ }
\DoxyCodeLine{01675\ \textcolor{comment}{/*\ Floating-\/Point\ Context\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01676\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_ASPEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 31U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01677\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_ASPEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_ASPEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01679\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPEN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 30U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01680\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPEN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_LSPEN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01682\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPENS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 29U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01683\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPENS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_LSPENS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01685\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_CLRONRET\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01686\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_CLRONRET\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_CLRONRET\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01687\ }
\DoxyCodeLine{01688\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_CLRONRETS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 27U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01689\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_CLRONRETS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_CLRONRETS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01691\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_TS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01692\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_TS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_TS\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01694\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_UFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 10U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01695\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_UFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_UFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01697\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_SPLIMVIOL\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ 9U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01698\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_SPLIMVIOL\_Msk\ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_SPLIMVIOL\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01699\ }
\DoxyCodeLine{01700\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MONRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01701\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MONRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_MONRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01703\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_SFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 7U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01704\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_SFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_SFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01706\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_BFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 6U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01707\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_BFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_BFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01709\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MMRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 5U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01710\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_MMRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_MMRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01711\ }
\DoxyCodeLine{01712\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_HFRDY\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01713\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_HFRDY\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_HFRDY\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01715\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_THREAD\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01716\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_THREAD\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_THREAD\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01717\ }
\DoxyCodeLine{01718\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_S\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 2U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01719\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_S\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_S\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01720\ }
\DoxyCodeLine{01721\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_USER\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 1U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01722\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_USER\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPCCR\_USER\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01724\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPACT\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01725\ \textcolor{preprocessor}{\#define\ FPU\_FPCCR\_LSPACT\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ }\textcolor{comment}{/*<<\ FPU\_FPCCR\_LSPACT\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01727\ \textcolor{comment}{/*\ Floating-\/Point\ Context\ Address\ Register\ Definitions\ */}}
\DoxyCodeLine{01728\ \textcolor{preprocessor}{\#define\ FPU\_FPCAR\_ADDRESS\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 3U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01729\ \textcolor{preprocessor}{\#define\ FPU\_FPCAR\_ADDRESS\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x1FFFFFFFUL\ <<\ FPU\_FPCAR\_ADDRESS\_Pos)\ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01731\ \textcolor{comment}{/*\ Floating-\/Point\ Default\ Status\ Control\ Register\ Definitions\ */}}
\DoxyCodeLine{01732\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_AHP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 26U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01733\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_AHP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPDSCR\_AHP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01735\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_DN\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 25U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01736\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_DN\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPDSCR\_DN\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01738\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_FZ\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01739\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_FZ\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (1UL\ <<\ FPU\_FPDSCR\_FZ\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01741\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_RMode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 22U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01742\ \textcolor{preprocessor}{\#define\ FPU\_FPDSCR\_RMode\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (3UL\ <<\ FPU\_FPDSCR\_RMode\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01744\ \textcolor{comment}{/*\ Media\ and\ FP\ Feature\ Register\ 0\ Definitions\ */}}
\DoxyCodeLine{01745\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_rounding\_modes\_Pos\ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01746\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_rounding\_modes\_Msk\ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_FP\_rounding\_modes\_Pos)\ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01748\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Short\_vectors\_Pos\ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01749\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Short\_vectors\_Msk\ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Short\_vectors\_Pos)\ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01751\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Square\_root\_Pos\ \ \ \ \ \ \ \ \ \ 20U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01752\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Square\_root\_Msk\ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Square\_root\_Pos)\ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01754\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Divide\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 16U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01755\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Divide\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Divide\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01757\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_excep\_trapping\_Pos\ \ \ \ 12U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01758\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_FP\_excep\_trapping\_Msk\ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_FP\_excep\_trapping\_Pos)\ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01760\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Double\_precision\_Pos\ \ \ \ \ \ 8U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01761\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Double\_precision\_Msk\ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Double\_precision\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01763\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Single\_precision\_Pos\ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01764\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_Single\_precision\_Msk\ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR0\_Single\_precision\_Pos)\ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01766\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_A\_SIMD\_registers\_Pos\ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01767\ \textcolor{preprocessor}{\#define\ FPU\_MVFR0\_A\_SIMD\_registers\_Msk\ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ FPU\_MVFR0\_A\_SIMD\_registers\_Pos*/}\textcolor{preprocessor}{)\ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01769\ \textcolor{comment}{/*\ Media\ and\ FP\ Feature\ Register\ 1\ Definitions\ */}}
\DoxyCodeLine{01770\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_fused\_MAC\_Pos\ \ \ \ \ \ \ \ \ 28U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01771\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_fused\_MAC\_Msk\ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR1\_FP\_fused\_MAC\_Pos)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01773\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_HPFP\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 24U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01774\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FP\_HPFP\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR1\_FP\_HPFP\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01776\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_D\_NaN\_mode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ 4U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01777\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_D\_NaN\_mode\_Msk\ \ \ \ \ \ \ \ \ \ \ (0xFUL\ <<\ FPU\_MVFR1\_D\_NaN\_mode\_Pos)\ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01779\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FtZ\_mode\_Pos\ \ \ \ \ \ \ \ \ \ \ \ \ \ 0U\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01780\ \textcolor{preprocessor}{\#define\ FPU\_MVFR1\_FtZ\_mode\_Msk\ \ \ \ \ \ \ \ \ \ \ \ \ (0xFUL\ }\textcolor{comment}{/*<<\ FPU\_MVFR1\_FtZ\_mode\_Pos*/}\textcolor{preprocessor}{)\ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01795\ \textcolor{keyword}{typedef}\ \textcolor{keyword}{struct}}
\DoxyCodeLine{01796\ \{}
\DoxyCodeLine{01797\ \ \ \_\_IOM\ uint32\_t\ DHCSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01798\ \ \ \_\_OM\ \ uint32\_t\ DCRSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01799\ \ \ \_\_IOM\ uint32\_t\ DCRDR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01800\ \ \ \_\_IOM\ uint32\_t\ DEMCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01801\ \ \ \ \ \ \ \ \ uint32\_t\ RESERVED4[1U];}
\DoxyCodeLine{01802\ \ \ \_\_IOM\ uint32\_t\ DAUTHCTRL;\ \ \ \ \ \ \ \ \ \ \ \ \ \ }
\DoxyCodeLine{01803\ \ \ \_\_IOM\ uint32\_t\ DSCSR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }
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\DoxyCodeLine{01967\ \textcolor{preprocessor}{\ \ \#define\ DWT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((DWT\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ DWT\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01968\ \textcolor{preprocessor}{\ \ \#define\ TPI\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((TPI\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ TPI\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01969\ \textcolor{preprocessor}{\ \ \#define\ CoreDebug\ \ \ \ \ \ \ \ \ \ \ ((CoreDebug\_Type\ *)\ \ \ \ \ CoreDebug\_BASE\ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01970\ }
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\DoxyCodeLine{01972\ \textcolor{preprocessor}{\ \ \ \ \#define\ MPU\_BASE\ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0D90UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01973\ \textcolor{preprocessor}{\ \ \ \ \#define\ MPU\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((MPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ MPU\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01974\ \textcolor{preprocessor}{\ \ \#endif}}
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\DoxyCodeLine{01977\ \textcolor{preprocessor}{\ \ \ \ \#define\ SAU\_BASE\ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0DD0UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01978\ \textcolor{preprocessor}{\ \ \ \ \#define\ SAU\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SAU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ SAU\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01981\ \textcolor{preprocessor}{\ \ \#define\ FPU\_BASE\ \ \ \ \ \ \ \ \ \ \ \ (SCS\_BASE\ +\ \ 0x0F30UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01982\ \textcolor{preprocessor}{\ \ \#define\ FPU\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((FPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ FPU\_BASE\ \ \ \ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
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\DoxyCodeLine{01985\ \textcolor{preprocessor}{\ \ \#define\ SCS\_BASE\_NS\ \ \ \ \ \ \ \ \ (0xE002E000UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01986\ \textcolor{preprocessor}{\ \ \#define\ CoreDebug\_BASE\_NS\ \ \ (0xE002EDF0UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01987\ \textcolor{preprocessor}{\ \ \#define\ SysTick\_BASE\_NS\ \ \ \ \ (SCS\_BASE\_NS\ +\ \ 0x0010UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01988\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_BASE\_NS\ \ \ \ \ \ \ \ (SCS\_BASE\_NS\ +\ \ 0x0100UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01989\ \textcolor{preprocessor}{\ \ \#define\ SCB\_BASE\_NS\ \ \ \ \ \ \ \ \ (SCS\_BASE\_NS\ +\ \ 0x0D00UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01990\ }
\DoxyCodeLine{01991\ \textcolor{preprocessor}{\ \ \#define\ SCnSCB\_NS\ \ \ \ \ \ \ \ \ \ \ ((SCnSCB\_Type\ \ \ \ *)\ \ \ \ \ SCS\_BASE\_NS\ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01992\ \textcolor{preprocessor}{\ \ \#define\ SCB\_NS\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SCB\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ SCB\_BASE\_NS\ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01993\ \textcolor{preprocessor}{\ \ \#define\ SysTick\_NS\ \ \ \ \ \ \ \ \ \ ((SysTick\_Type\ \ \ *)\ \ \ \ \ SysTick\_BASE\_NS\ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01994\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_NS\ \ \ \ \ \ \ \ \ \ \ \ \ ((NVIC\_Type\ \ \ \ \ \ *)\ \ \ \ \ NVIC\_BASE\_NS\ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01995\ \textcolor{preprocessor}{\ \ \#define\ CoreDebug\_NS\ \ \ \ \ \ \ \ ((CoreDebug\_Type\ *)\ \ \ \ \ CoreDebug\_BASE\_NS)\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{01996\ }
\DoxyCodeLine{01997\ \textcolor{preprocessor}{\ \ \#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}}
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\DoxyCodeLine{01999\ \textcolor{preprocessor}{\ \ \ \ \#define\ MPU\_NS\ \ \ \ \ \ \ \ \ \ \ \ ((MPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ MPU\_BASE\_NS\ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02000\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02001\ }
\DoxyCodeLine{02002\ \textcolor{preprocessor}{\ \ \#define\ FPU\_BASE\_NS\ \ \ \ \ \ \ \ \ (SCS\_BASE\_NS\ +\ \ 0x0F30UL)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02003\ \textcolor{preprocessor}{\ \ \#define\ FPU\_NS\ \ \ \ \ \ \ \ \ \ \ \ \ \ ((FPU\_Type\ \ \ \ \ \ \ *)\ \ \ \ \ FPU\_BASE\_NS\ \ \ \ \ \ )\ }\textcolor{preprocessor}{}}
\DoxyCodeLine{02004\ }
\DoxyCodeLine{02005\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{02007\ }
\DoxyCodeLine{02008\ }
\DoxyCodeLine{02009\ }
\DoxyCodeLine{02010\ \textcolor{comment}{/*******************************************************************************}}
\DoxyCodeLine{02011\ \textcolor{comment}{\ *\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Hardware\ Abstraction\ Layer}}
\DoxyCodeLine{02012\ \textcolor{comment}{\ \ Core\ Function\ Interface\ contains:}}
\DoxyCodeLine{02013\ \textcolor{comment}{\ \ -\/\ Core\ NVIC\ Functions}}
\DoxyCodeLine{02014\ \textcolor{comment}{\ \ -\/\ Core\ SysTick\ Functions}}
\DoxyCodeLine{02015\ \textcolor{comment}{\ \ -\/\ Core\ Debug\ Functions}}
\DoxyCodeLine{02016\ \textcolor{comment}{\ \ -\/\ Core\ Register\ Access\ Functions}}
\DoxyCodeLine{02017\ \textcolor{comment}{\ ******************************************************************************/}}
\DoxyCodeLine{02021\ }
\DoxyCodeLine{02022\ }
\DoxyCodeLine{02023\ }
\DoxyCodeLine{02024\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ NVIC\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02031\ }
\DoxyCodeLine{02032\ \textcolor{preprocessor}{\#ifdef\ CMSIS\_NVIC\_VIRTUAL}}
\DoxyCodeLine{02033\ \textcolor{preprocessor}{\ \ \#ifndef\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{02034\ \textcolor{preprocessor}{\ \ \ \ \#define\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE\ "{}cmsis\_nvic\_virtual.h"{}}}
\DoxyCodeLine{02035\ \textcolor{preprocessor}{\ \ \#endif}}
\DoxyCodeLine{02036\ \textcolor{preprocessor}{\ \ \#include\ CMSIS\_NVIC\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{02037\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02038\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPriorityGrouping\ \ \ \ \_\_NVIC\_SetPriorityGrouping}}
\DoxyCodeLine{02039\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPriorityGrouping\ \ \ \ \_\_NVIC\_GetPriorityGrouping}}
\DoxyCodeLine{02040\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_EnableIRQ\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_EnableIRQ}}
\DoxyCodeLine{02041\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetEnableIRQ\ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetEnableIRQ}}
\DoxyCodeLine{02042\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_DisableIRQ\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_DisableIRQ}}
\DoxyCodeLine{02043\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPendingIRQ\ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetPendingIRQ}}
\DoxyCodeLine{02044\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPendingIRQ\ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SetPendingIRQ}}
\DoxyCodeLine{02045\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_ClearPendingIRQ\ \ \ \ \ \ \ \ \_\_NVIC\_ClearPendingIRQ}}
\DoxyCodeLine{02046\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetActive\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetActive}}
\DoxyCodeLine{02047\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetPriority\ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SetPriority}}
\DoxyCodeLine{02048\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetPriority\ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetPriority}}
\DoxyCodeLine{02049\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SystemReset\ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SystemReset}}
\DoxyCodeLine{02050\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ CMSIS\_NVIC\_VIRTUAL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02051\ }
\DoxyCodeLine{02052\ \textcolor{preprocessor}{\#ifdef\ CMSIS\_VECTAB\_VIRTUAL}}
\DoxyCodeLine{02053\ \textcolor{preprocessor}{\ \ \#ifndef\ CMSIS\_VECTAB\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{02054\ \textcolor{preprocessor}{\ \ \ \ \#define\ CMSIS\_VECTAB\_VIRTUAL\_HEADER\_FILE\ "{}cmsis\_vectab\_virtual.h"{}}}
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\DoxyCodeLine{02056\ \textcolor{preprocessor}{\ \ \#include\ CMSIS\_VECTAB\_VIRTUAL\_HEADER\_FILE}}
\DoxyCodeLine{02057\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02058\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_SetVector\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_SetVector}}
\DoxyCodeLine{02059\ \textcolor{preprocessor}{\ \ \#define\ NVIC\_GetVector\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_NVIC\_GetVector}}
\DoxyCodeLine{02060\ \textcolor{preprocessor}{\#endif\ \ }\textcolor{comment}{/*\ (CMSIS\_VECTAB\_VIRTUAL)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02061\ }
\DoxyCodeLine{02062\ \textcolor{preprocessor}{\#define\ NVIC\_USER\_IRQ\_OFFSET\ \ \ \ \ \ \ \ \ \ 16}}
\DoxyCodeLine{02063\ }
\DoxyCodeLine{02064\ }
\DoxyCodeLine{02065\ \textcolor{comment}{/*\ Special\ LR\ values\ for\ Secure/Non-\/Secure\ call\ handling\ and\ exception\ handling\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02066\ }
\DoxyCodeLine{02067\ \textcolor{comment}{/*\ Function\ Return\ Payload\ (from\ ARMv8-\/M\ Architecture\ Reference\ Manual)\ LR\ value\ on\ entry\ from\ Secure\ BLXNS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}\ }
\DoxyCodeLine{02068\ \textcolor{preprocessor}{\#define\ FNC\_RETURN\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0xFEFFFFFFUL)\ \ \ \ \ }\textcolor{comment}{/*\ bit\ [0]\ ignored\ when\ processing\ a\ branch\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02069\ }
\DoxyCodeLine{02070\ \textcolor{comment}{/*\ The\ following\ EXC\_RETURN\ mask\ values\ are\ used\ to\ evaluate\ the\ LR\ on\ exception\ entry\ */}}
\DoxyCodeLine{02071\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_PREFIX\ \ \ \ \ \ \ \ \ \ (0xFF000000UL)\ \ \ \ \ }\textcolor{comment}{/*\ bits\ [31:24]\ set\ to\ indicate\ an\ EXC\_RETURN\ value\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02072\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_S\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000040UL)\ \ \ \ \ }\textcolor{comment}{/*\ bit\ [6]\ stack\ used\ to\ push\ registers:\ 0=Non-\/secure\ 1=Secure\ \ \ \ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02073\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_DCRS\ \ \ \ \ \ \ \ \ \ \ \ (0x00000020UL)\ \ \ \ \ }\textcolor{comment}{/*\ bit\ [5]\ stacking\ rules\ for\ called\ registers:\ 0=skipped\ 1=saved\ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02074\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_FTYPE\ \ \ \ \ \ \ \ \ \ \ (0x00000010UL)\ \ \ \ \ }\textcolor{comment}{/*\ bit\ [4]\ allocate\ stack\ for\ floating-\/point\ context:\ 0=done\ 1=skipped\ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02075\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_MODE\ \ \ \ \ \ \ \ \ \ \ \ (0x00000008UL)\ \ \ \ \ }\textcolor{comment}{/*\ bit\ [3]\ processor\ mode\ for\ return:\ 0=Handler\ mode\ 1=Thread\ mode\ \ \ \ \ \ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{02077\ \textcolor{preprocessor}{\#define\ EXC\_RETURN\_ES\ \ \ \ \ \ \ \ \ \ \ \ \ \ (0x00000001UL)\ \ \ \ \ }\textcolor{comment}{/*\ bit\ [0]\ security\ state\ exception\ was\ taken\ to:\ 0=Non-\/secure\ 1=Secure\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{02079\ \textcolor{comment}{/*\ Integrity\ Signature\ (from\ ARMv8-\/M\ Architecture\ Reference\ Manual)\ for\ exception\ context\ stacking\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02080\ \textcolor{preprocessor}{\#if\ defined\ (\_\_FPU\_PRESENT)\ \&\&\ (\_\_FPU\_PRESENT\ ==\ 1U)\ \ }\textcolor{comment}{/*\ Value\ for\ processors\ with\ floating-\/point\ extension:\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02081\ \textcolor{preprocessor}{\#define\ EXC\_INTEGRITY\_SIGNATURE\ \ \ \ \ (0xFEFA125AUL)\ \ \ \ \ }\textcolor{comment}{/*\ bit\ [0]\ SFTC\ must\ match\ LR\ bit[4]\ EXC\_RETURN\_FTYPE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{02083\ \textcolor{preprocessor}{\#define\ EXC\_INTEGRITY\_SIGNATURE\ \ \ \ \ (0xFEFA125BUL)\ \ \ \ \ }\textcolor{comment}{/*\ Value\ for\ processors\ without\ floating-\/point\ extension\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{02085\ }
\DoxyCodeLine{02086\ }
\DoxyCodeLine{02096\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \_\_NVIC\_SetPriorityGrouping(uint32\_t\ PriorityGroup)}
\DoxyCodeLine{02097\ \{}
\DoxyCodeLine{02098\ \ \ uint32\_t\ reg\_value;}
\DoxyCodeLine{02099\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02100\ }
\DoxyCodeLine{02101\ \ \ reg\_value\ \ =\ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ read\ old\ register\ configuration\ \ \ \ */}}
\DoxyCodeLine{02102\ \ \ reg\_value\ \&=\ \string~((uint32\_t)(\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga90c7cf0c490e7ae55f9503a7fda1dd22}{SCB\_AIRCR\_VECTKEY\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}}));\ \textcolor{comment}{/*\ clear\ bits\ to\ change\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02103\ \ \ reg\_value\ \ =\ \ (reg\_value\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |}
\DoxyCodeLine{02104\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ |}
\DoxyCodeLine{02105\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (PriorityGroupTmp\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaca155deccdeca0f2c76b8100d24196c8}{SCB\_AIRCR\_PRIGROUP\_Pos}})\ \ );\ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Insert\ write\ key\ and\ priority\ group\ */}}
\DoxyCodeLine{02106\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ =\ \ reg\_value;}
\DoxyCodeLine{02107\ \}}
\DoxyCodeLine{02108\ }
\DoxyCodeLine{02109\ }
\DoxyCodeLine{02115\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core_debug_gae1de06155d072758b3453edb07d12459}{\_\_NVIC\_GetPriorityGrouping}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02116\ \{}
\DoxyCodeLine{02117\ \ \ \textcolor{keywordflow}{return}\ ((uint32\_t)((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ >>\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaca155deccdeca0f2c76b8100d24196c8}{SCB\_AIRCR\_PRIGROUP\_Pos}}));}
\DoxyCodeLine{02118\ \}}
\DoxyCodeLine{02119\ }
\DoxyCodeLine{02120\ }
\DoxyCodeLine{02127\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga71227e1376cde11eda03fcb62f1b33ea}{\_\_NVIC\_EnableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02128\ \{}
\DoxyCodeLine{02129\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02130\ \ \ \{}
\DoxyCodeLine{02131\ \ \ \ \ \_\_COMPILER\_BARRIER();}
\DoxyCodeLine{02132\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02133\ \ \ \ \ \_\_COMPILER\_BARRIER();}
\DoxyCodeLine{02134\ \ \ \}}
\DoxyCodeLine{02135\ \}}
\DoxyCodeLine{02136\ }
\DoxyCodeLine{02137\ }
\DoxyCodeLine{02146\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaaeb5e7cc0eaad4e2817272e7bf742083}{\_\_NVIC\_GetEnableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02147\ \{}
\DoxyCodeLine{02148\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02149\ \ \ \{}
\DoxyCodeLine{02150\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02151\ \ \ \}}
\DoxyCodeLine{02152\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02153\ \ \ \{}
\DoxyCodeLine{02154\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02155\ \ \ \}}
\DoxyCodeLine{02156\ \}}
\DoxyCodeLine{02157\ }
\DoxyCodeLine{02158\ }
\DoxyCodeLine{02165\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gae016e4c1986312044ee768806537d52f}{\_\_NVIC\_DisableIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02166\ \{}
\DoxyCodeLine{02167\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02168\ \ \ \{}
\DoxyCodeLine{02169\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ICER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02170\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02171\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gaad233022e850a009fc6f7602be1182f6}{\_\_ISB}}();}
\DoxyCodeLine{02172\ \ \ \}}
\DoxyCodeLine{02173\ \}}
\DoxyCodeLine{02174\ }
\DoxyCodeLine{02175\ }
\DoxyCodeLine{02184\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga5a92ca5fa801ad7adb92be7257ab9694}{\_\_NVIC\_GetPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02185\ \{}
\DoxyCodeLine{02186\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02187\ \ \ \{}
\DoxyCodeLine{02188\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02189\ \ \ \}}
\DoxyCodeLine{02190\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02191\ \ \ \{}
\DoxyCodeLine{02192\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02193\ \ \ \}}
\DoxyCodeLine{02194\ \}}
\DoxyCodeLine{02195\ }
\DoxyCodeLine{02196\ }
\DoxyCodeLine{02203\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaabefdd4b790b9a7308929938c0c1e1ad}{\_\_NVIC\_SetPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02204\ \{}
\DoxyCodeLine{02205\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02206\ \ \ \{}
\DoxyCodeLine{02207\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02208\ \ \ \}}
\DoxyCodeLine{02209\ \}}
\DoxyCodeLine{02210\ }
\DoxyCodeLine{02211\ }
\DoxyCodeLine{02218\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga562a86dbdf14827d0fee8fdafb04d191}{\_\_NVIC\_ClearPendingIRQ}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02219\ \{}
\DoxyCodeLine{02220\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02221\ \ \ \{}
\DoxyCodeLine{02222\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ICPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02223\ \ \ \}}
\DoxyCodeLine{02224\ \}}
\DoxyCodeLine{02225\ }
\DoxyCodeLine{02226\ }
\DoxyCodeLine{02235\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaa2837003c28c45abf193fe5e8d27f593}{\_\_NVIC\_GetActive}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02236\ \{}
\DoxyCodeLine{02237\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02238\ \ \ \{}
\DoxyCodeLine{02239\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IABR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02240\ \ \ \}}
\DoxyCodeLine{02241\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02242\ \ \ \{}
\DoxyCodeLine{02243\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02244\ \ \ \}}
\DoxyCodeLine{02245\ \}}
\DoxyCodeLine{02246\ }
\DoxyCodeLine{02247\ }
\DoxyCodeLine{02248\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02257\ \_\_STATIC\_INLINE\ uint32\_t\ NVIC\_GetTargetState(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02258\ \{}
\DoxyCodeLine{02259\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02260\ \ \ \{}
\DoxyCodeLine{02261\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ITNS[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02262\ \ \ \}}
\DoxyCodeLine{02263\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02264\ \ \ \{}
\DoxyCodeLine{02265\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02266\ \ \ \}}
\DoxyCodeLine{02267\ \}}
\DoxyCodeLine{02268\ }
\DoxyCodeLine{02269\ }
\DoxyCodeLine{02278\ \_\_STATIC\_INLINE\ uint32\_t\ NVIC\_SetTargetState(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02279\ \{}
\DoxyCodeLine{02280\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02281\ \ \ \{}
\DoxyCodeLine{02282\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ITNS[(((uint32\_t)IRQn)\ >>\ 5UL)]\ |=\ \ ((uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)));}
\DoxyCodeLine{02283\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ITNS[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02284\ \ \ \}}
\DoxyCodeLine{02285\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02286\ \ \ \{}
\DoxyCodeLine{02287\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02288\ \ \ \}}
\DoxyCodeLine{02289\ \}}
\DoxyCodeLine{02290\ }
\DoxyCodeLine{02291\ }
\DoxyCodeLine{02300\ \_\_STATIC\_INLINE\ uint32\_t\ NVIC\_ClearTargetState(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02301\ \{}
\DoxyCodeLine{02302\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02303\ \ \ \{}
\DoxyCodeLine{02304\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ITNS[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&=\ \string~((uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)));}
\DoxyCodeLine{02305\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>ITNS[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02306\ \ \ \}}
\DoxyCodeLine{02307\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02308\ \ \ \{}
\DoxyCodeLine{02309\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02310\ \ \ \}}
\DoxyCodeLine{02311\ \}}
\DoxyCodeLine{02312\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02313\ }
\DoxyCodeLine{02314\ }
\DoxyCodeLine{02324\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga505338e23563a9c074910fb14e7d45fd}{\_\_NVIC\_SetPriority}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ priority)}
\DoxyCodeLine{02325\ \{}
\DoxyCodeLine{02326\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02327\ \ \ \{}
\DoxyCodeLine{02328\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IPR[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{02329\ \ \ \}}
\DoxyCodeLine{02330\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02331\ \ \ \{}
\DoxyCodeLine{02332\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHPR[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{02333\ \ \ \}}
\DoxyCodeLine{02334\ \}}
\DoxyCodeLine{02335\ }
\DoxyCodeLine{02336\ }
\DoxyCodeLine{02346\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gaeb9dc99c8e7700668813144261b0bc73}{\_\_NVIC\_GetPriority}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02347\ \{}
\DoxyCodeLine{02348\ }
\DoxyCodeLine{02349\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02350\ \ \ \{}
\DoxyCodeLine{02351\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gac8e97e8ce56ae9f57da1363a937f8a17}{NVIC}}-\/>IPR[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{02352\ \ \ \}}
\DoxyCodeLine{02353\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02354\ \ \ \{}
\DoxyCodeLine{02355\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>SHPR[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{02356\ \ \ \}}
\DoxyCodeLine{02357\ \}}
\DoxyCodeLine{02358\ }
\DoxyCodeLine{02359\ }
\DoxyCodeLine{02371\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_gadb94ac5d892b376e4f3555ae0418ebac}{NVIC\_EncodePriority}}\ (uint32\_t\ PriorityGroup,\ uint32\_t\ PreemptPriority,\ uint32\_t\ SubPriority)}
\DoxyCodeLine{02372\ \{}
\DoxyCodeLine{02373\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02374\ \ \ uint32\_t\ PreemptPriorityBits;}
\DoxyCodeLine{02375\ \ \ uint32\_t\ SubPriorityBits;}
\DoxyCodeLine{02376\ }
\DoxyCodeLine{02377\ \ \ PreemptPriorityBits\ =\ ((7UL\ -\/\ PriorityGroupTmp)\ >\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ ?\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ :\ (uint32\_t)(7UL\ -\/\ PriorityGroupTmp);}
\DoxyCodeLine{02378\ \ \ SubPriorityBits\ \ \ \ \ =\ ((PriorityGroupTmp\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ <\ (uint32\_t)7UL)\ ?\ (uint32\_t)0UL\ :\ (uint32\_t)((PriorityGroupTmp\ -\/\ 7UL)\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}));}
\DoxyCodeLine{02379\ }
\DoxyCodeLine{02380\ \ \ \textcolor{keywordflow}{return}\ (}
\DoxyCodeLine{02381\ \ \ \ \ \ \ \ \ \ \ \ ((PreemptPriority\ \&\ (uint32\_t)((1UL\ <<\ (PreemptPriorityBits))\ -\/\ 1UL))\ <<\ SubPriorityBits)\ |}
\DoxyCodeLine{02382\ \ \ \ \ \ \ \ \ \ \ \ ((SubPriority\ \ \ \ \ \&\ (uint32\_t)((1UL\ <<\ (SubPriorityBits\ \ \ \ ))\ -\/\ 1UL)))}
\DoxyCodeLine{02383\ \ \ \ \ \ \ \ \ \ );}
\DoxyCodeLine{02384\ \}}
\DoxyCodeLine{02385\ }
\DoxyCodeLine{02386\ }
\DoxyCodeLine{02398\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga3387607fd8a1a32cccd77d2ac672dd96}{NVIC\_DecodePriority}}\ (uint32\_t\ Priority,\ uint32\_t\ PriorityGroup,\ uint32\_t*\ \textcolor{keyword}{const}\ pPreemptPriority,\ uint32\_t*\ \textcolor{keyword}{const}\ pSubPriority)}
\DoxyCodeLine{02399\ \{}
\DoxyCodeLine{02400\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02401\ \ \ uint32\_t\ PreemptPriorityBits;}
\DoxyCodeLine{02402\ \ \ uint32\_t\ SubPriorityBits;}
\DoxyCodeLine{02403\ }
\DoxyCodeLine{02404\ \ \ PreemptPriorityBits\ =\ ((7UL\ -\/\ PriorityGroupTmp)\ >\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ ?\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ :\ (uint32\_t)(7UL\ -\/\ PriorityGroupTmp);}
\DoxyCodeLine{02405\ \ \ SubPriorityBits\ \ \ \ \ =\ ((PriorityGroupTmp\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ <\ (uint32\_t)7UL)\ ?\ (uint32\_t)0UL\ :\ (uint32\_t)((PriorityGroupTmp\ -\/\ 7UL)\ +\ (uint32\_t)(\mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}));}
\DoxyCodeLine{02406\ }
\DoxyCodeLine{02407\ \ \ *pPreemptPriority\ =\ (Priority\ >>\ SubPriorityBits)\ \&\ (uint32\_t)((1UL\ <<\ (PreemptPriorityBits))\ -\/\ 1UL);}
\DoxyCodeLine{02408\ \ \ *pSubPriority\ \ \ \ \ =\ (Priority\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ )\ \&\ (uint32\_t)((1UL\ <<\ (SubPriorityBits\ \ \ \ ))\ -\/\ 1UL);}
\DoxyCodeLine{02409\ \}}
\DoxyCodeLine{02410\ }
\DoxyCodeLine{02411\ }
\DoxyCodeLine{02421\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga0df355460bc1783d58f9d72ee4884208}{\_\_NVIC\_SetVector}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ vector)}
\DoxyCodeLine{02422\ \{}
\DoxyCodeLine{02423\ \ \ uint32\_t\ *vectors\ =\ (uint32\_t\ *)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>VTOR;}
\DoxyCodeLine{02424\ \ \ vectors[(int32\_t)IRQn\ +\ NVIC\_USER\_IRQ\_OFFSET]\ =\ vector;}
\DoxyCodeLine{02425\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();}
\DoxyCodeLine{02426\ \}}
\DoxyCodeLine{02427\ }
\DoxyCodeLine{02428\ }
\DoxyCodeLine{02437\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga44b665d2afb708121d9b10c76ff00ee5}{\_\_NVIC\_GetVector}}(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02438\ \{}
\DoxyCodeLine{02439\ \ \ uint32\_t\ *vectors\ =\ (uint32\_t\ *)\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>VTOR;}
\DoxyCodeLine{02440\ \ \ \textcolor{keywordflow}{return}\ vectors[(int32\_t)IRQn\ +\ NVIC\_USER\_IRQ\_OFFSET];}
\DoxyCodeLine{02441\ \}}
\DoxyCodeLine{02442\ }
\DoxyCodeLine{02443\ }
\DoxyCodeLine{02448\ \_\_NO\_RETURN\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga0d9aa2d30fa54b41eb780c16e35b676c}{\_\_NVIC\_SystemReset}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02449\ \{}
\DoxyCodeLine{02450\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Ensure\ all\ outstanding\ memory\ accesses\ included}}
\DoxyCodeLine{02451\ \textcolor{comment}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ buffered\ write\ are\ completed\ before\ reset\ */}}
\DoxyCodeLine{02452\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \ =\ (uint32\_t)((0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ \ \ \ |}
\DoxyCodeLine{02453\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaaf6477c2bde2f00f99e3c2fd1060b01}{SCB}}-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ |}
\DoxyCodeLine{02454\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaae1181119559a5bd36e62afa373fa720}{SCB\_AIRCR\_SYSRESETREQ\_Msk}}\ \ \ \ );\ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Keep\ priority\ group\ unchanged\ */}}
\DoxyCodeLine{02455\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_ga067d257a2b34565410acefb5afef2203}{\_\_DSB}}();\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Ensure\ completion\ of\ memory\ access\ */}}
\DoxyCodeLine{02456\ }
\DoxyCodeLine{02457\ \ \ \textcolor{keywordflow}{for}(;;)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ wait\ until\ reset\ */}}
\DoxyCodeLine{02458\ \ \ \{}
\DoxyCodeLine{02459\ \ \ \ \ \mbox{\hyperlink{group___c_m_s_i_s___core___instruction_interface_gabd585ddc865fb9b7f2493af1eee1a572}{\_\_NOP}}();}
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\DoxyCodeLine{02461\ \}}
\DoxyCodeLine{02462\ }
\DoxyCodeLine{02463\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02473\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_SetPriorityGrouping\_NS(uint32\_t\ PriorityGroup)}
\DoxyCodeLine{02474\ \{}
\DoxyCodeLine{02475\ \ \ uint32\_t\ reg\_value;}
\DoxyCodeLine{02476\ \ \ uint32\_t\ PriorityGroupTmp\ =\ (PriorityGroup\ \&\ (uint32\_t)0x07UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ only\ values\ 0..7\ are\ used\ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02477\ }
\DoxyCodeLine{02478\ \ \ reg\_value\ \ =\ \ SCB\_NS-\/>AIRCR;\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ read\ old\ register\ configuration\ \ \ \ */}}
\DoxyCodeLine{02479\ \ \ reg\_value\ \&=\ \string~((uint32\_t)(\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga90c7cf0c490e7ae55f9503a7fda1dd22}{SCB\_AIRCR\_VECTKEY\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}}));\ \textcolor{comment}{/*\ clear\ bits\ to\ change\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02480\ \ \ reg\_value\ \ =\ \ (reg\_value\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ |}
\DoxyCodeLine{02481\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)0x5FAUL\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaaa27c0ba600bf82c3da08c748845b640}{SCB\_AIRCR\_VECTKEY\_Pos}})\ |}
\DoxyCodeLine{02482\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (PriorityGroupTmp\ <<\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaca155deccdeca0f2c76b8100d24196c8}{SCB\_AIRCR\_PRIGROUP\_Pos}})\ \ );\ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Insert\ write\ key\ and\ priority\ group\ */}}
\DoxyCodeLine{02483\ \ \ SCB\_NS-\/>AIRCR\ =\ \ reg\_value;}
\DoxyCodeLine{02484\ \}}
\DoxyCodeLine{02485\ }
\DoxyCodeLine{02486\ }
\DoxyCodeLine{02492\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_NVIC\_GetPriorityGrouping\_NS(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02493\ \{}
\DoxyCodeLine{02494\ \ \ \textcolor{keywordflow}{return}\ ((uint32\_t)((SCB\_NS-\/>AIRCR\ \&\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga8be60fff03f48d0d345868060dc6dae7}{SCB\_AIRCR\_PRIGROUP\_Msk}})\ >>\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gaca155deccdeca0f2c76b8100d24196c8}{SCB\_AIRCR\_PRIGROUP\_Pos}}));}
\DoxyCodeLine{02495\ \}}
\DoxyCodeLine{02496\ }
\DoxyCodeLine{02497\ }
\DoxyCodeLine{02504\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_EnableIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02505\ \{}
\DoxyCodeLine{02506\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02507\ \ \ \{}
\DoxyCodeLine{02508\ \ \ \ \ NVIC\_NS-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02509\ \ \ \}}
\DoxyCodeLine{02510\ \}}
\DoxyCodeLine{02511\ }
\DoxyCodeLine{02512\ }
\DoxyCodeLine{02521\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_NVIC\_GetEnableIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02522\ \{}
\DoxyCodeLine{02523\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02524\ \ \ \{}
\DoxyCodeLine{02525\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((NVIC\_NS-\/>ISER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02526\ \ \ \}}
\DoxyCodeLine{02527\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02528\ \ \ \{}
\DoxyCodeLine{02529\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02530\ \ \ \}}
\DoxyCodeLine{02531\ \}}
\DoxyCodeLine{02532\ }
\DoxyCodeLine{02533\ }
\DoxyCodeLine{02540\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_DisableIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02541\ \{}
\DoxyCodeLine{02542\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02543\ \ \ \{}
\DoxyCodeLine{02544\ \ \ \ \ NVIC\_NS-\/>ICER[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02545\ \ \ \}}
\DoxyCodeLine{02546\ \}}
\DoxyCodeLine{02547\ }
\DoxyCodeLine{02548\ }
\DoxyCodeLine{02557\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_NVIC\_GetPendingIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02558\ \{}
\DoxyCodeLine{02559\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02560\ \ \ \{}
\DoxyCodeLine{02561\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((NVIC\_NS-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02562\ \ \ \}}
\DoxyCodeLine{02563\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02564\ \ \ \{}
\DoxyCodeLine{02565\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02566\ \ \ \}}
\DoxyCodeLine{02567\ \}}
\DoxyCodeLine{02568\ }
\DoxyCodeLine{02569\ }
\DoxyCodeLine{02576\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_SetPendingIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02577\ \{}
\DoxyCodeLine{02578\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02579\ \ \ \{}
\DoxyCodeLine{02580\ \ \ \ \ NVIC\_NS-\/>ISPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02581\ \ \ \}}
\DoxyCodeLine{02582\ \}}
\DoxyCodeLine{02583\ }
\DoxyCodeLine{02584\ }
\DoxyCodeLine{02591\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_ClearPendingIRQ\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02592\ \{}
\DoxyCodeLine{02593\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02594\ \ \ \{}
\DoxyCodeLine{02595\ \ \ \ \ NVIC\_NS-\/>ICPR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ =\ (uint32\_t)(1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL));}
\DoxyCodeLine{02596\ \ \ \}}
\DoxyCodeLine{02597\ \}}
\DoxyCodeLine{02598\ }
\DoxyCodeLine{02599\ }
\DoxyCodeLine{02608\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_NVIC\_GetActive\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02609\ \{}
\DoxyCodeLine{02610\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02611\ \ \ \{}
\DoxyCodeLine{02612\ \ \ \ \ \textcolor{keywordflow}{return}((uint32\_t)(((NVIC\_NS-\/>IABR[(((uint32\_t)IRQn)\ >>\ 5UL)]\ \&\ (1UL\ <<\ (((uint32\_t)IRQn)\ \&\ 0x1FUL)))\ !=\ 0UL)\ ?\ 1UL\ :\ 0UL));}
\DoxyCodeLine{02613\ \ \ \}}
\DoxyCodeLine{02614\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02615\ \ \ \{}
\DoxyCodeLine{02616\ \ \ \ \ \textcolor{keywordflow}{return}(0U);}
\DoxyCodeLine{02617\ \ \ \}}
\DoxyCodeLine{02618\ \}}
\DoxyCodeLine{02619\ }
\DoxyCodeLine{02620\ }
\DoxyCodeLine{02630\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_NVIC\_SetPriority\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn,\ uint32\_t\ priority)}
\DoxyCodeLine{02631\ \{}
\DoxyCodeLine{02632\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02633\ \ \ \{}
\DoxyCodeLine{02634\ \ \ \ \ NVIC\_NS-\/>IPR[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{02635\ \ \ \}}
\DoxyCodeLine{02636\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02637\ \ \ \{}
\DoxyCodeLine{02638\ \ \ \ \ SCB\_NS-\/>SHPR[(((uint32\_t)IRQn)\ \&\ 0xFUL)-\/4UL]\ =\ (uint8\_t)((priority\ <<\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}}))\ \&\ (uint32\_t)0xFFUL);}
\DoxyCodeLine{02639\ \ \ \}}
\DoxyCodeLine{02640\ \}}
\DoxyCodeLine{02641\ }
\DoxyCodeLine{02642\ }
\DoxyCodeLine{02651\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_NVIC\_GetPriority\_NS(\mbox{\hyperlink{group___peripheral__interrupt__number__definition_ga7e1129cd8a196f4284d41db3e82ad5c8}{IRQn\_Type}}\ IRQn)}
\DoxyCodeLine{02652\ \{}
\DoxyCodeLine{02653\ }
\DoxyCodeLine{02654\ \ \ \textcolor{keywordflow}{if}\ ((int32\_t)(IRQn)\ >=\ 0)}
\DoxyCodeLine{02655\ \ \ \{}
\DoxyCodeLine{02656\ \ \ \ \ \textcolor{keywordflow}{return}(((uint32\_t)NVIC\_NS-\/>IPR[((uint32\_t)IRQn)]\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ >>\ (8U\ -\/\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})));}
\DoxyCodeLine{02657\ \ \ \}}
\DoxyCodeLine{02658\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02659\ \ \ \{}
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\DoxyCodeLine{02662\ \}}
\DoxyCodeLine{02663\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&(\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02664\ }
\DoxyCodeLine{02666\ }
\DoxyCodeLine{02667\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ MPU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02668\ }
\DoxyCodeLine{02669\ \textcolor{preprocessor}{\#if\ defined\ (\_\_MPU\_PRESENT)\ \&\&\ (\_\_MPU\_PRESENT\ ==\ 1U)}}
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\DoxyCodeLine{02671\ \textcolor{preprocessor}{\#include\ "{}mpu\_armv8.h"{}}}
\DoxyCodeLine{02672\ }
\DoxyCodeLine{02673\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02674\ }
\DoxyCodeLine{02675\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ FPU\ functions\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
\DoxyCodeLine{02682\ }
\DoxyCodeLine{02691\ \_\_STATIC\_INLINE\ uint32\_t\ \mbox{\hyperlink{group___c_m_s_i_s___core___n_v_i_c_functions_ga6bcad99ce80a0e7e4ddc6f2379081756}{SCB\_GetFPUType}}(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02692\ \{}
\DoxyCodeLine{02693\ \ \ uint32\_t\ mvfr0;}
\DoxyCodeLine{02694\ }
\DoxyCodeLine{02695\ \ \ mvfr0\ =\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gabc7c93f2594e85ece1e1a24f10591428}{FPU}}-\/>MVFR0;}
\DoxyCodeLine{02696\ \ \ \textcolor{keywordflow}{if}\ \ \ \ \ \ ((mvfr0\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga95008f205c9d25e4ffebdbdc50d5ae44}{FPU\_MVFR0\_Single\_precision\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga3f2c8c6c759ffe70f548a165602ea901}{FPU\_MVFR0\_Double\_precision\_Msk}}))\ ==\ 0x220U)}
\DoxyCodeLine{02697\ \ \ \{}
\DoxyCodeLine{02698\ \ \ \ \ \textcolor{keywordflow}{return}\ 2U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Double\ +\ Single\ precision\ FPU\ */}}
\DoxyCodeLine{02699\ \ \ \}}
\DoxyCodeLine{02700\ \ \ \textcolor{keywordflow}{else}\ \textcolor{keywordflow}{if}\ ((mvfr0\ \&\ (\mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga95008f205c9d25e4ffebdbdc50d5ae44}{FPU\_MVFR0\_Single\_precision\_Msk}}\ |\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga3f2c8c6c759ffe70f548a165602ea901}{FPU\_MVFR0\_Double\_precision\_Msk}}))\ ==\ 0x020U)}
\DoxyCodeLine{02701\ \ \ \{}
\DoxyCodeLine{02702\ \ \ \ \ \textcolor{keywordflow}{return}\ 1U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Single\ precision\ FPU\ */}}
\DoxyCodeLine{02703\ \ \ \}}
\DoxyCodeLine{02704\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{02705\ \ \ \{}
\DoxyCodeLine{02706\ \ \ \ \ \textcolor{keywordflow}{return}\ 0U;\ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ No\ FPU\ */}}
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\DoxyCodeLine{02708\ \}}
\DoxyCodeLine{02709\ }
\DoxyCodeLine{02710\ }
\DoxyCodeLine{02712\ }
\DoxyCodeLine{02713\ }
\DoxyCodeLine{02714\ }
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\DoxyCodeLine{02723\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}}
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\DoxyCodeLine{02729\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_SAU\_Enable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02730\ \{}
\DoxyCodeLine{02731\ \ \ \ \ SAU-\/>CTRL\ |=\ \ (SAU\_CTRL\_ENABLE\_Msk);}
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\DoxyCodeLine{02733\ }
\DoxyCodeLine{02734\ }
\DoxyCodeLine{02735\ }
\DoxyCodeLine{02740\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ TZ\_SAU\_Disable(\textcolor{keywordtype}{void})}
\DoxyCodeLine{02741\ \{}
\DoxyCodeLine{02742\ \ \ \ \ SAU-\/>CTRL\ \&=\ \string~(SAU\_CTRL\_ENABLE\_Msk);}
\DoxyCodeLine{02743\ \}}
\DoxyCodeLine{02744\ }
\DoxyCodeLine{02745\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{02748\ }
\DoxyCodeLine{02749\ }
\DoxyCodeLine{02750\ }
\DoxyCodeLine{02751\ }
\DoxyCodeLine{02752\ \textcolor{comment}{/*\ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ \ \ \ SysTick\ function\ \ \#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\#\ */}}
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\DoxyCodeLine{02760\ \textcolor{preprocessor}{\#if\ defined\ (\_\_Vendor\_SysTickConfig)\ \&\&\ (\_\_Vendor\_SysTickConfig\ ==\ 0U)}}
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\DoxyCodeLine{02776\ \ \ \{}
\DoxyCodeLine{02777\ \ \ \ \ \textcolor{keywordflow}{return}\ (1UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Reload\ value\ impossible\ */}}
\DoxyCodeLine{02778\ \ \ \}}
\DoxyCodeLine{02779\ }
\DoxyCodeLine{02780\ \ \ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_gacd96c53beeaff8f603fcda425eb295de}{SysTick}}-\/>LOAD\ \ =\ (uint32\_t)(ticks\ -\/\ 1UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ set\ reload\ register\ */}}
\DoxyCodeLine{02781\ \ \ NVIC\_SetPriority\ (\mbox{\hyperlink{group___peripheral__interrupt__number__definition_gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7}{SysTick\_IRQn}},\ (1UL\ <<\ \mbox{\hyperlink{group___configuration__section__for___c_m_s_i_s_gae3fe3587d5100c787e02102ce3944460}{\_\_NVIC\_PRIO\_BITS}})\ -\/\ 1UL);\ \textcolor{comment}{/*\ set\ Priority\ for\ Systick\ Interrupt\ */}}
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\DoxyCodeLine{02786\ \ \ \textcolor{keywordflow}{return}\ (0UL);\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \textcolor{comment}{/*\ Function\ successful\ */}}
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\DoxyCodeLine{02788\ }
\DoxyCodeLine{02789\ \textcolor{preprocessor}{\#if\ defined\ (\_\_ARM\_FEATURE\_CMSE)\ \&\&\ (\_\_ARM\_FEATURE\_CMSE\ ==\ 3U)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02802\ \_\_STATIC\_INLINE\ uint32\_t\ TZ\_SysTick\_Config\_NS(uint32\_t\ ticks)}
\DoxyCodeLine{02803\ \{}
\DoxyCodeLine{02804\ \ \ \textcolor{keywordflow}{if}\ ((ticks\ -\/\ 1UL)\ >\ \mbox{\hyperlink{group___c_m_s_i_s___c_o_r_e_ga265912a7962f0e1abd170336e579b1b1}{SysTick\_LOAD\_RELOAD\_Msk}})}
\DoxyCodeLine{02805\ \ \ \{}
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